make file for compiling c and c++ in linux

 Let's understand with an example:

Suppose, we have 3 files 

    main.c (main source file),

    misc.c (source file that contains function definition), 

    misc.h (that contain function declaration). 

Here we will declare and define a function named myFunc() to print something –

 this function will be defined and declared in misc.c and misc.h respectively.

misc.c

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#include <stdio.h> #include "misc.h"   /*function definition*/ void myFunc(void) {     printf("Body of myFunc function.\n"); }

misc.h

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#ifndef MISC_H     #define MISC_H           /*function declaration.*/     void myFunc(void);       #endif

main.c

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#include <stdio.h> #include "misc.h"   int main() {     printf("Hello, World.\n");     myFunc();     fflush(stdout);       return 0; }

Makefile to compile these files

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#make file - this is a comment section   all:    #target name     gcc main.c misc.c -o main

• Save file with name "Makefile".
• Insert comment followed by # character.
• all is a target name, insert : after target name.
• gcc is compiler name, main.c, misc.c source file names, -o is linker flag and main is binary file name.

Compile program/project using Makefile

Command make is used to compile program through Makefile, since there are only one target all in the Makefile, so we do not need to mention target name because first target is got compiled automatically.

Without target name:

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make

With target name:

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make all

Output:

    sh-4.3$ make
    gcc     main.c misc.c -o main

    sh-4.3$ ./main
    Hello, World.

    Body of myFunc function.
    sh-4.3$

Makefile using variables and clean target

We can also use variables in the Makefile to generalise Makefile. In this examples we are writing Makefile using variables and clean target name to remove all object (.o extension files) and binary file (main).

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#make file - this is a comment section   CC=gcc  #compiler TARGET=main #target file name   all:     $(CC) main.c misc.c -o $(TARGET)   clean:     rm $(TARGET)

To compile:

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make

To clean:

1	make clean

Output:

    sh-4.3$ make
    gcc     main.c misc.c -o main

    sh-4.3$ ./main
    Hello, World.
    Body of myFunc function.

    sh-4.3$ make clean
    rm main
    sh-4.3$

Makefile with creating Object of source files and Cleaning Object files and Binary File

When we have multiple files then we can write command in Makefile to create Object files for each source file. If you do this – Only those files will be compiled which are modified.

Makefile

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#make file - this is a comment section   CC=gcc  #compiler TARGET=main #target file name   all:    main.o misc.o     $(CC) main.c misc.c -o $(TARGET)   clean:     rm *.o $(TARGET)

Output: When main.c and misc.c modified

    sh-4.3$ make
    gcc     -c -o main.o main.c
    gcc     -c -o misc.o misc.c
    gcc     main.c misc.c -o main

Output: When main.c modified

    sh-4.3$ make
    gcc     -c -o main.o main.c
    gcc     main.c misc.c -o main

Output: When misc.c modified

    sh-4.3$ make
    gcc     -c -o misc.o misc.c
    gcc     main.c misc.c -o main

Output: When no file modified

    sh-4.3$ make
    gcc     main.c misc.c -o main

What is rm *.o $(TARGET) ?

This command will remove all object files with along with TARGET file that is main.